Free Inside the Machine: An Illustrated Introduction to Microprocessors and Computer Architecture by jon stokes Page B

zero or
    nonzero, positive or negative, and so on.
    Different architectures handle this in different ways, but in our DLW-1,
    this is the function of the processor status word (PSW) register. On the DLW-1, every arithmetic operation stores different types of data about its outcome in
    the PSW upon completion. To execute a conditional branch, the DLW-1
    must first evaluate the condition on which the branch depends (e.g., “is the previous arithmetic instruction’s result zero?” in the preceding example) by
    checking the appropriate bit in the PSW to see if that condition is true or
    false. If the branch condition evaluates to true, then the control unit replaces the address in the program counter with the branch target address. If the
    branch condition evaluates to false, then the program counter is left as-is,
    and the next instruction in the normal program sequence is fetched on the
    next cycle.
    For example, suppose we had just subtracted the number in A from the
    number in B, and if the result was zero (that is, if the two numbers were equal), we want to jump to the instruction at memory address #106. Program 2-2
    shows what assembler code for such a conditional branch might look like.
    Line
    Code
    Comments
    16
    sub A, B, C
    Subtract the number in register A from the number in register B and
    store the result in C.
    17
    jumpz #106
    Check the PSW, and if the result of the previous instruction was zero,
    jump to the instruction at address #106. If the result was nonzero,
    continue on to line 18.
    18
    add A, B, C
    Add the numbers in registers A and B and store the result in C.
    Program 2-2: Assembler code for a conditional branch
    The jumpz instruction causes the processor to check the PSW to determine
    whether a certain bit is 1 (true) or 0 (false). If the bit is 1, the result of the subtraction instruction was 0 and the program counter must be loaded with
    the branch target address. If the bit is 0, the program counter is incremented
    to point to the next instruction in sequence (which is the add instruction in
    line 18).
    There are other bits in the PSW that specify other types of information
    about the result of the previous operation (whether it is positive or negative,
    is too large for the registers to hold, and so on). As such, there are also other The Mechanics of Program Execution
    31
    types of conditional branch instructions that check these bits. For instance,
    the jumpn instruction jumps to the target address if the result of the preceding arithmetic operation was negative; the jumpo instruction jumps to the target
    address if the result of the previous operation was too large and overflowed
    the register. If the machine language instruction format of the DLW-1 could
    accommodate more than eight possible instructions, we could add more
    types of conditional jumps.
    Branch Instructions and the Fetch-Execute Loop
    Now that we have looked at the basics of branching, we can modify our three-
    step summary of program execution to include the possibility of a branch
    instruction:
    1.
    Fetch the next instruction from the address stored in the program
    counter, and load that instruction into the instruction register.
    Increment the program counter.
    2.
    Decode the instruction in the instruction register.
    3.
    Execute the instruction in the instruction register, using the following rules:
    a.
    If the instruction is an arithmetic instruction, then execute it using
    the ALU and register file.
    b.
    If the instruction is a memory-access instruction, then execute it
    using the memory hardware.
    c.
    If the instruction is a branch instruction, then execute it using the
    control unit and the program counter. (For a taken branch, write
    the branch target address into the program counter.)
    In short, you might say that branch instructions allow the programmer to
    redirect the processor as it travels through the instruction stream. Branches
    point the processor to different sections of the code stream by manipulating
    its control